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    <title>OpenSIL on Thoughts dereferenced from the scratchpad noise.</title>
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      <title>MSI PRO B850-P coreboot port: Phoenix openSIL AM5 IP block porting</title>
      <link>https://beta.blog.3mdeb.com/2026/2026-04-03-msi_pro_b850p_part3/</link>
      <pubDate>Fri, 03 Apr 2026 00:00:00 +0000</pubDate>
      
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      <description>Introduction This blog post continues the MSI PRO B850-P coreboot porting series. In Part 1 we brought up the bootblock and romstage, mapped all USB, SATA, and PCIe ports. In Part 2 we added the USB and PCIe devicetree descriptors and integrated Phoenix openSIL as a submodule, reaching CCX initialization successfully - but the platform stalled during PCIe initialization because the Phoenix PoC openSIL was written for mobile CPUs, not the desktop AM5 variant used on the B850-P.</description>
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      <title>MSI PRO B850-P coreboot port: PCIe and USB descriptors and Phoenix OpenSIL</title>
      <link>https://beta.blog.3mdeb.com/2026/2026-03-06-msi_pro_b850p_part2/</link>
      <pubDate>Fri, 06 Mar 2026 00:00:00 +0000</pubDate>
      
      <guid>https://beta.blog.3mdeb.com/2026/2026-03-06-msi_pro_b850p_part2/</guid>
      <description>Introduction This blog post continues where Part 1 left off. As a quick recap: we successfully brought up bootblock and romstage on the MSI PRO B850-P using coreboot, but ramstage halted waiting for CPU core initialization that depends on OpenSIL. We also mapped all USB, SATA, and PCIe ports during the hardware-topology discovery phase.
Before diving into the new content, there is one important development to mention: all Dasharo code has been rebased from coreboot 24.</description>
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